Systems and methods herein generally relate to image processors and image processing and more particularly to image enlargement and reduction in, for example, simultaneous duplex magnification compensation processes for high-speed software image path (SWIP) applications.
Simultaneous duplex (two-sided) scanning uses a document feeder that can scan both sides of a page at once by moving the document past two individual scan modules. The document feeder employs a constant velocity transport (CVT) to move the document past the stationary scan stations, thereby reducing the time for copying or scanning 2-sided originals. Unfortunately, the mechanical design and optics of each scanning station are not exact and can therefore generate subtle, fast-scan magnification differences between the two sides of the document. Although these magnification differences are relatively small and difficult to observe when comparing the rendered prints, high-end devices generally require that the two sides generate equivalent image quality with respect to the front and backside originals, especially for certain situations. The need to adjust for these small magnification differences is therefore very useful.
Therefore, in duplex scanning and copy applications, there are slight magnification differences between the front and backside of the captured images due to variations in optics, mechanical tolerances, etc., and additional scaling adjustments are performed to precisely match the two sides. This is known as duplex magnification compensation (DMC). Traditional scaling processes, however, process each side in its entirety (adjust the magnification of every pixel) even when only subtle magnification adjustments are required. Depending upon the scaling process selected, the amount of calculations required to achieve a 9% image reduction, for example, can be as extensive as 0.1% reduction. Although generally not an issue in hardware, duplex magnification compensation can consume precious processor cycles to simply apply side 1-to-side 2 scaling adjustments (which can be as small as +/−1%) and can therefore significantly degrade overall SWIP performance.
Image scaling is commonly performed in hardware (field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.) mainly because lower-cost microprocessors available in the past could not achieve the rated speeds used by advanced classes of copy/print reprographic machines. However, for the next generation of office multi-function device (MFD) products, there are plans to leverage the latest competitive multi-core processors in order to offer a more robust and flexible image-path architecture. To that end, a software-based image path (SWIP) solution is actively being developed to replace the traditional hardware-based solution. The development of new image-processing techniques are therefore useful in order to provide an efficient, high-speed copy path solution by leveraging the capabilities of advanced processors.